FIG. 1 illustrates a typical example 100 of the main steps involved in integrated circuit (IC) design. The example illustrated in FIG. 1 starts with a generation 110 of a register transfer level (RTL) description for an operation of an IC being designed. In the RTL description, a circuit's behaviour is defined in terms of a flow of signals (or transfer of data) between, say, hardware registers, and the logic operations performed on those signals. Logic synthesis 120 is then performed, whereby the RTL description is mapped into a cell-level net list in the target technology. Placement and routing 130 of the cells in the net list is then performed, where the cells are assigned to non-overlapping locations on the die area, and the interconnecting tracks are routed through the various layers of the semiconductor die. Static timing analysis (STA) 140 is then performed to verify that all signals will arrive within their intended time frames, and to detect possible ‘hold time’ violations, setup time violations, slow paths, clock skew, etc. Once static timing analysis has been performed, post routing leakage optimisation 150 is performed. Post routing leakage optimisation comprises identifying timing paths with positive slack and attempts to reduce current leakage on that path without creating a timing violation.
During logic synthesis 120, the RTL description is mapped into a cell-level net list by selecting appropriate cells from one or more libraries of cells. A typical standard cell definition library is a collection of low-level logic functions, such as AND, OR INVERT, flip-flops, latches, buffers, etc. These cells are realized as fixed height, variable width cells. A key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated layout. Each library typically contains multiple implementations of the same logic function(s), with each cell of a specific logic function differing in area (width) and speed. In order to achieve optimal performance for an IC that is being designed, it is generally the case that high speed cells, for example relatively large, low threshold voltage cells, are selected during logic synthesis as the initial, default cells. The advantage of using such high speed cells as the initial default cells is that they provide high performance and thereby enable higher operating frequencies of the integrated circuit. However, a drawback of low voltage threshold cells is that they generally suffer from high leakage currents. With the continued progress in process scaling, leakage power consumption has become an increasingly important factor in the overall power consumption of an integrated circuit device. Reducing the leakage power consumption (and thereby the overall power consumption) of an integrated circuit device is important for a number of reasons, including: lower requirements for external power supplies; more compact SoC (System on Chip) power grid, which in turn leads to higher routing resources, reduced die size and thereby a cheaper product; reduced power dissipation requirements for the IC package, and thereby cheaper packaging; etc.
Thus, a net result of reducing the leakage power consumption of an integrated circuit device is not just of reduced overall power consumption of the device, but also a significantly cheaper cost of materials for customers. Thus, the step of leakage optimisation 150 is an increasingly important part of the integrated circuit design process. Post routing leakage optimisation is particularly important in terms of reducing leakage power consumption, without impacting on the performance or operation of the integrated circuit device, and is typically performed in addition to other power reduction techniques, such as lowering stand-by voltages, performance versus process and temperature compensation, power gating and state retention power gating techniques, back biasing, etc.
Typically, post routing leakage optimisation involves identifying timing paths with positive adjustable margin, and substituting one or more cells within those timing paths with lower leakage cells of the same type. Although the lower leakage cells are ‘slower’ in terms of their propagation times (e.g. a length of time from receiving a signal to that signal propagating there through and its product being presented at an output thereof), the positive adjustable margins of the identified timing path enables such substitutions to be made without causing a timing violation.
Generally, such post routing leakage optimisation comprises substituting one or more cells within an identified timing path with:                (i) smaller (i.e. reduced transistor width) versions of the one or more cell(s) creating the timing problem; and/or        (ii) higher voltage threshold versions of the cells(s).        
A problem with this approach is that, due to the different size of the cells, it is necessary for the tracks corresponding to the substituted cells to be re-routed, as illustrated at re-routing step 160 in FIG. 1, and for static timing analysis to be repeated 170. The need to perform re-routing 160 and thereafter to repeat the static timing analysis 170 means that the date on which tapeout 180 may be achieved (i.e. the final result of the design cycle for the IC, where the artwork for the photomask of the IC is sent for manufacture) is significantly delayed, as illustrated generally at 190. Any such delay in the development of a product is undesirable.
To overcome the problem of needing to perform re-routing 160 and to repeat static timing analysis 170, it is known for the step of post routing leakage optimisation to only comprise substituting one or more cells within an identified timing path with cells comprising higher voltage thresholds, since such cells are typically of the same size (width) as the lower voltage threshold versions of the same cell. Accordingly, the need for re-routing may be avoided. However, whilst substituting higher voltage threshold cells does enable leakage current to be reduced without the need for perform rerouting 160 and to repeat static timing analysis 170, further reductions in the leakage currents of cells within identified timing paths is desirable.